logic synthesis造句
例句与造句
- Logic synthesis logic synthesizer
逻辑合成逻辑合成器 - ( 4 ) design and implement the alogrithm " delay balance in multiple level logic synthesis "
( 4 )设计并实现了“多级逻辑综合延迟均衡”算法。 - 2 . the logic synthesis process is studied in detail and the relative constraints are discussed
2 .详细研究了soc应用设计流程中的逻辑综合技术方法。 - 2002 , 149 : 119 - 128 . 9 sasao t . switching theory for logic synthesis . kluwer academic publishers , london , 1999
通过对给定的fprm真值矢量进行收缩,获得收缩后的真值矢量,然后把该矢量映射成逻辑表示式。 - This dissertation detailedly investigate the symbolic logic and some typical techniques for low power fsm logic synthesis and optimization
论文详细讨论了低功耗有限状态机综合与优化中的符号逻辑和一些典型方法。 - It's difficult to find logic synthesis in a sentence. 用logic synthesis造句挺难的
- Finally , their applications in the logic synthesis based on the partial linear function and calculating boolean difference of logical functions are discussed
最后讨论了它们在逻辑综合以及计算逻辑函数的布尔差分中的应用。 - Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description
逻辑综合的功能是对组合逻辑函数的描述进行转换和优化，生成与逻辑功能描述等价的优化的逻辑级纯结构描述。 - At last , the paper involves the flow and related data of logic simulation , logic synthesis and test vector in the risc cpu
论文最后给出了64位vegacpu的asic逻辑仿真文件和仿真波形，逻辑综合策略、综合脚本和综合结果，以及vegacpu基于atpg的测试向量设计流程和相关数据。 - The design phase includes the standardization of rtl coding , logic synthesis and place & route ; the verification phase includes the function verification , static timing analysis and physical verification for 08c01
设计工作包括对08c01软核的rtl级代码标准化、逻辑综合和布局布线；验证工作包括对08c01软核的功能验证、静态时序分析和物理验证。 - By the top - down way , the design was divided into several modules according to their functions , which were characterized respectively . meanwhile , behavior description , rtl function simulation and logic synthesis were carried out
在充分了解驱动电路系统的基础上,采用“自上向下”的设计方法将其划分为几个功能模块,并对它们分别进行了行为描述、 rtl功能仿真、逻辑综合。 - The fourth chapter is the implementation part of carrier recovery in asic , including structure division , hardware design logic synthesis and verification . the asic design skills oriented to synthesis and dft ( design for test ) are discussed in the end
第四章给出载波同步在asic设计中的具体实现，包括结构划分、硬件设计、逻辑综合和验证等，最后讨论了面向综合的asic设计技巧和可测性设计。 - Except for design methodology and technique , some comprehensive experiments are performed . these experiments use some eda tools , including functional simulation with cadence ' s verilog xl , logic synthesis with synopsys ' s design compiler
本文除了介绍的设计方法和设计技巧，还做了一些有益的实验，使用到许多流行的eda工具，如cadence公司的verilog - xl 、 siliconensemble ， synopsys公司的designcompiler 、 physicalcompiler等。 - High - level synthesis has been developed on the base of logic synthesis . it starts from the behavioral design description of high - level and outputs the structural description with lower level as a result . so the design complexity can be simplified and design efficiency can be raised
高级综合是在逻辑综合的基础上发展而来的，它从高层次的行为描述开始，自动综合出低层次的结构描述，从而降低了设计复杂度，提高了设计效率。 - This paper focuses on the combitional logic synthesis including two level logic synthesis and multiple level synthesis . and it is a part of control flow synthesis in a controller synthesis system . in this paper following problems are proposed and implemented : ( 1 ) implement the algorithm " espresso " , and make it suit to the system
本文所完成的组合逻辑综合的研究与实现是控制流综合系统的一个组成部分，其中包括： ( 1 )引入并实现了两级逻辑综合的“ espresso ”算法，定义与系统相适应的数据结构，重新测试各种开关条件，使之适用于系统的实际应用。 - 26th ieee asilomar conference on signals , systems , and computers , pacific grove , ca , usa , october 26 - 28 , 1992 , pp . 391 - 395 . 14 oklobdzija v . an algorithmic and novel design of a leading zero detector circuit : comparison with logic synthesis . ieee transactions on vlsi systems , 1993 , 2 : 124 - 128
而另一方面，该算法与目前国际上其它类似算法相比具有面积和功耗上的明显优势，根据实验结果，采用该算法所实现的电路面积比采用以往类似算法所实现的电路面积减少了27 ，功耗则降低了28 ，因此特别适合在高性能低功耗的浮点加减运算算法中采用。
更多例句： 下一页